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this is information on a product in full production. february 2016 docid024225 rev 6 1/41 M95040-A125 m95040-a145 automotive 4-kbit serial spi bus eeproms with high-speed clock datasheet - production data features ? compatible with the serial peripheral interface (spi) bus ? memory array ? 4 kbit (512 byte) of eeprom ? page size: 16 byte ? write protection by bl ock: 1/4, 1/2 or whole memory ? additional write lockable page (identification page) ? extended temperature and voltage ranges ? up to 125 c (v cc from 1.7 v to 5.5 v) ? up to 145 c (v cc from 2.5 v to 5.5 v) ? high speed clock frequency ? 20 mhz for v cc 4.5 v ? 10 mhz for v cc 2.5 v ? 5 mhz for v cc 1.7 v ? schmitt trigger inputs for noise filtering ? short write cycle time ? byte write within 4 ms ? page write within 4 ms ? write cycle endurance ? 4 million write cycles at 25 c ? 1.2 million write cycles at 85 c ? 600 k write cycles at 125 c ? 400 k write cycles at 145 c ? data retention ? 50 years at 125 c ? 100 years at 25 c ? esd protection (human body model) ? 4000 v ? packages ? rohs-compliant and halogen-free (ecopack2 ? ) tssop8 (dw) 169 mil width so8 (mn) 150 mil width wfdfpn8 (mf) 2 x 3 mm www.st.com
contents M95040-A125 m95040-a145 2/41 docid024225 rev 6 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 serial data output (q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 serial data input (d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 serial clock (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 chip select (s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 hold (hold ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6 write protect (w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.7 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.8 v cc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 hold mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.4 protocol control and data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.4.1 protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4.2 status register and data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 write enable (wren) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 write disable (wrdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 read status register (rdsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.4 write status register (wrsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.5 read from memory array (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.6 write to memory array (write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.7 read identification page (rdid) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.8 write identification page (wrid) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.9 read lock status (rdls) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.10 lock identification page (lid) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
docid024225 rev 6 3/41 M95040-A125 m95040-a145 contents 3 5 application design recommendati ons . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1.1 operating supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1.2 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1.3 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2 implementing devices on spi bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3 error correction code (ecc x 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6 delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.1 so8n package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.2 tssop8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.3 wfdfpn8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
list of tables M95040-A125 m95040-a145 4/41 docid024225 rev 6 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4. device identification bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 5. instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 6. significant bits within the address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 7. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 8. cycling performance by byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 9. operating conditions (voltage range w, temperature range 4). . . . . . . . . . . . . . . . . . . . . . 28 table 10. operating conditions (voltage range r, temperature range 3) . . . . . . . . . . . . . . . . . . . . . . 28 table 11. operating conditions (volt age range r, temperature range 3) for high-speed communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 12. dc characteristics (voltage range w, temperature range 4). . . . . . . . . . . . . . . . . . . . . . . . 29 table 13. dc characteristics (voltage range r, temperature range 3) . . . . . . . . . . . . . . . . . . . . . . . . 30 table 14. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 15. so8n ? 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 16. tssop8 ? 8-lead thin shrink sm all outline, 3 x 4.4 mm, 0.65 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 17. wfpn8 (mlp8) ? 8-lead, 2 x 3 mm, 0.5 mm pitch very very thin fine pitch dual flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 18. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 19. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
docid024225 rev 6 5/41 M95040-A125 m95040-a145 list of figures 5 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. spi modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. hold mode activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. write enable (wren) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 figure 6. write disable (wrdi) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 7. read status register (rdsr) se quence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 8. write status register (wrsr) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 9. read from memory array (read) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 10. byte write (write) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 11. page write (write) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 12. read identification page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 13. write identification page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 14. read lock status sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 15. lock id sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 16. bus master and memory devices on the spi bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 17. ac measurement i/o wa veform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 18. serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 19. hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 20. serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 21. so8n ? 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 34 figure 22. so8n ? 8-lead plastic small outline, 150 mils body width, package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 23. tssop8 ? 8-lead thin shrink sm all outline, 3 x 4.4 mm, 0.65 mm pitch, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 24. wfdfpn8 (mlp8) ? 8-lead, 2 x 3 mm, 0.5 mm pitch very very thin fine pitch dual flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
description M95040-A125 m95040-a145 6/41 docid024225 rev 6 1 description the M95040-A125 and m95040-a 145 are 4-kbit serial eeprom automotive grade devices operating up to 145c. they ar e compliant with the very high level of reliability defined by the automotive standard aec-q100 grade 0. the devices are accessed by a simple seri al spi compatible interface running up to 20 mhz. the memory array is based on advanced true eeprom technology (elect rically erasable programmable memory). the M95040-A125 and m95040-a145 are byte-alterable memories (512 8 bits) organized as 32 pages of 16 byte in which the data integrity is significantly improved with an embedded error correction code logic. the M95040-A125 and m95040-a145 offer an addi tional identification page (16 byte) in which the st device identification can be re ad. this page can also be used to store sensitive application parameters which can be later permanently locked in read-only mode. figure 1. logic diagram 069 ,k> ^ t }v??}oo}p] ,]pz}o?p pv??}? /lk?z](??p]??? ????p]??? v}v?? ? ?p]??? ?p y}? z}? y ^]}(?z z}vo? wzkd ? ^??? ?p]??? /v?](]?]}v?p le l?
docid024225 rev 6 7/41 M95040-A125 m95040-a145 description 40 figure 2. 8-pin package connections 1. see package mechanical data section for package dimensions and how to identify pin-1. table 1. signal names signal name description c serial clock d serial data input q serial data output s chip select w write protect hold hold v cc supply voltage v ss ground $ 6 33 # (/,$ 1 36 ## 7 !)$ -xxx
signal description M95040-A125 m95040-a145 8/41 docid024225 rev 6 2 signal description all input signals must be held high or low (according to voltages of v ih or v il , as specified in table 12 and table 13 ). these signals are described below. 2.1 serial data output (q) this output signal is used to transfer data serially out of the device during a read operation. data is shifted out on the falling edge of serial clock (c), most significant bit (m sb) first. in all other cases, the serial data output is in high impedance. 2.2 serial data input (d) this input signal is used to transfer data serially into the device. d input receives instructions, addresses, and the data to be writ ten. values are latched on the rising edge of serial clock (c), most significant bit (msb) first. 2.3 serial clock (c) this input signal allows to sy nchronize the timing of the se rial interface. instructions, addresses, or data present at serial data input (d) are latched on the rising edge of serial clock (c). data on serial data output (q) changes after the falling edge of serial clock (c). 2.4 chip select (s ) driving chip select ( s ) low selects the device in order to start communication. driving chip select ( s ) high deselects the device and serial da ta output (q) enters the high impedance state. 2.5 hold (hold ) the hold ( hold ) signal is used to pause any serial communications with the device without deselecting the device. during the hold condition, the serial data output (q) is high impedance, and the serial data input (d) and serial clock (c) are don?t care. to start the hold condition, the device must be sele cted, with chip select (s) driven low. 2.6 write protect (w ) this pin is used to write-protect the status register. 2.7 v ss ground v ss is the reference for all signals, including the v cc supply voltage.
docid024225 rev 6 9/41 M95040-A125 m95040-a145 signal description 40 2.8 v cc supply voltage v cc is the supply voltage pin. refer to section 3.1: active power and standby power modes and to section 5.1: supply voltage (vcc) .
operating features M95040-A125 m95040-a145 10/41 docid024225 rev 6 3 operating features 3.1 active power and standby power modes when chip select ( s ) is low, the device is selected and in the active power mode. when chip select ( s ) is high, the device is deselected. if a write cycle is not currently in progress, the device then goes in to the stan dby power mode, and the device consumption drops to i cc1 , as specified in table 12 and table 13 . 3.2 spi modes the device can be driven by a microcontroller wit h its spi peripheral running in either of the two following modes: ? cpol=0, cpha=0 ? cpol=1, cpha=1 for these two modes, input data is latched in on the rising edge of serial clock (c), and output data is available from t he falling edge of serial clock (c). the difference between the two modes, as shown in figure 3 , is the clock polarity when the bus master is in stand-by mode and not transferring data: ? c remains at 0 for (cpol=0, cpha=0) ? c remains at 1 for (cpol=1, cpha=1) figure 3. spi modes supported !)" # -3" #0(! $ #0/, 1 # -3"
docid024225 rev 6 11/41 M95040-A125 m95040-a145 operating features 40 3.3 hold mode the hold ( hold ) signal is used to pause any serial communications with the device without resetting the clocking sequence. the hold mode starts when the hold ( hold ) signal is driven low and the serial clock (c) is low (as shown in figure 4 ). during the hold mode, the se rial data output (q) is high impedance, and the signals present on serial data input (d) and serial clock (c) are not decoded. the hold mode ends when the hold ( hold ) signal is driven high and the serial clock (c) is or becomes low. figure 4. hold mode activation deselecting the device while it is in hold mode resets the paused communication. 3.4 protocol control and data protection 3.4.1 protocol control the chip select ( s ) input offers a built-in safety feature, as the s input is edge-sensitive as well as level-sensitive: after po wer-up, the device is not select ed until a falling edge has first been detected on chip select ( s ). this ensures that chip select ( s ) must have been high prior to going low, in order to start the first operation. for write commands (write, wrsr, wrid, lid) to be accepted and executed: ? the write enable latch (wel) bit must be se t by a write enable (wren) instruction ? a falling edge and a low st ate on chip select (s ) during the whole command must be decoded ? instruction, address and input data must be sent as multiple of eight bits ? the command must include at least one data byte ? chip select (s ) must be driven high exactly after a data byte boundary write command can be discarded at any time by a rising edge on chip select ( s ) outside of a byte boundary. to execute read commands (read, rdsr, rdid, rdls), the device must decode: ? a falling edge and a low level on chip select (s ) during the whole command ? instruction and address as multiples of eight bits (byte) from this step, data bits are shifted out until the rising edge on chip select ( s ). (/,$ # (old condition # onditio n (old condition -36
operating features M95040-A125 m95040-a145 12/41 docid024225 rev 6 3.4.2 status register and data protection the status register format is shown in table 2 and the status and control bits of the status register are as follows: note: bits b7, b6, b5 and b4 are always read as 1 . wip bit the wip bit (write in progress) is a read-only flag that indicates the ready/busy state of the device. when a write command (write, wrsr, wrid, lid) has been decoded and a write cycle (t w ) is in progress, the device is busy and the wip bit is set to 1. when wip=0, the device is ready to decode a new command. during a write cycle, reading continuously th e wip bit allows to detect when the device becomes ready (wip=0) to decode a new command. wel bit the wel bit (write enable latch) bit is a flag that indicates the status of the internal write enable latch. when wel is set to 1, the writ e instructions (write, wrsr, wrid, lid) are executed; when wel is set to 0, any decoded write instruction is not executed. the wel bit is set to 1 with the wren instru ction. the wel bit is reset to 0 after the following events: ? write disable (wrdi) instruction completion ? write instructions (write, wrsr, wrid, li d) completion including the write cycle time t w ? power-up bp1, bp0 bits the block protect bits (bp1, bp0) are non-vol atile. bp1,bp0 bits define the size of the memory block to be protected against write instructions, as defined in table 2 . these bits are written with the write status register (wrsr) instruction. table 2. status register format b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 1 bp1 bp0 wel wip block protect bits write enable latch bit write in progress bit
docid024225 rev 6 13/41 M95040-A125 m95040-a145 operating features 40 3.5 identification page the M95040-A125 and m95040-a145 offer an identification page (16 byte) in addition to the 4 kbit memory. the identification page contains two fields: ? device identification: the three first byte are programmed by stmicroelectronics with the device identification code, as shown in table 4 . ? application parameters: the bytes after the de vice identification code are available for application specific data. note: if the end application does not need to read the device identification code, this field can be overwritten and used to store application-spec ific data. once the app lication-specific data are written in the identification page, the whol e identification page should be permanently locked in read-only mode. the read, write, lock identificati on page instructions are detailed in section 4: instructions . table 3. write-protected block size status register bits protected block protected array addresses bp1 bp0 0 0 none none 0 1 upper quarter 180h-1ffh 1 0 upper half 100h - 1ffh 1 1 whole memory 000h - 1ffh plus identification page table 4. device id entification bytes address in identification page content value 00h st manufacturer code 20h 01h spi family code 00h 02h memory density code 09h (4 kbit)
instructions M95040-A125 m95040-a145 14/41 docid024225 rev 6 4 instructions each command is composed of bytes (msbit tran smitted first), initiate d with the instruction byte, as summarized in table 5 . if an invalid instruction is sent (one not contained in table 5 ), the device automatically enters a wait state until deselected. for read and write commands to memory array and identification page, the address is defined by two bytes as explained in table 6 . table 5. instruction set instruction description instruction format wren write enable 0000 x110 (1) 1. x = don?t care. wrdi write disable 0000 x100 (1) rdsr read status register 0000 x101 (1) wrsr write status register 0000 x001 (1) read read from memory array 0000 a 8 011 (2) 2. a8 = 1 for the upper half of the memory array, and 0 for the lower half. write write to memory array 0000 a 8 010 (2) rdid read identification page 1000 0011 wrid write identification page 1000 0010 rdls reads the identification page lock status. 1000 0011 lid locks the identific ation page in read- only mode. 1000 0010 table 6. significant bits within the address byte (1)(2) instructions bit b3 of the instruction byte lsb address byte b7 b6 b5 b4 b3 b2 b1 b0 read or write xxxxxxxa8a7a6a5a4a3a2a1a0 rdid or wrid 00000000000a4a3a2a1a0 rdls or lid 0000000010000000 1. a: significant address bit. 2. x: bit is don?t care.
docid024225 rev 6 15/41 M95040-A125 m95040-a145 instructions 40 4.1 write enable (wren) the wren instruction must be decoded by t he device before a write instruction (write, wrsr, wrid or lid). as shown in figure 5 , to send this instruction to the device, chip select ( s ) is driven low, the bits of the instruction byte are shifted in (msb first) on serial data input (d) after what the chip select ( s ) input is driven high and the wel bit is set (status register bit). figure 5. write enable (wren) sequence 4.2 write disable (wrdi) one way of resetting the wel bit (in the st atus register) is to send a write disable instruction to the device. as shown in figure 6 , to send this instruction to the device, chip select ( s ) is driven low, and the bits of the instruction byte are shifted in (msb first), on serial data input (d), after what the chip select ( s ) input is driven high and the wel bit is reset (status register bit). if a write cycle is currently in progress, the w rdi instruction is dec oded and executed and the wel bit is reset to 0 with no effect on the ongoing write cycle. in fact, the write enable latch (wel) bit be comes reset by any of the following events: ? power-up ? wrdi instruction execution ? wrsr instruction completion ? write instruction completion ? write protect (w) line being held low. dlyj ^ y ? ?e? ,]pz/u?v /v????]}v
instructions M95040-A125 m95040-a145 16/41 docid024225 rev 6 figure 6. write disable (wrdi) sequence 4.3 read status register (rdsr) the read status register (rdsr) instruction is used to read the content of the status register. as shown in figure 7 , to send this instruction to the device, chip select ( s ) is first driven low. the bits of the instruction byte are shift ed in (msb first) on serial data input (d), the status register content is then shifted ou t (msb first) on serial data output (q). if chip select ( s ) continues to be driven low, the stat us register content is continuously shifted out. the status register can always be read, even if a write cycle (t w ) is in progress. the status register functionality is detailed in section 3.4.2: status register and data protection . figure 7. read status register (rdsr) sequence # $ !)d 3 1 (igh)mpedance )nstruction # $ 3 )nstruction !)% 1 3tatus2egister/ut (igh)mpedance -3" 3tatus2egister/ut -3"
docid024225 rev 6 17/41 M95040-A125 m95040-a145 instructions 40 4.4 write status register (wrsr) the write status register (wrsr) instruction allows new values to be written to the status register. before it can be accepted, a write enable (wren) instruct ion must previously have been executed. the write status register (wrsr) instruction is entered (msb fi rst) by driving chip select ( s ) low, sending the instruction code followed by the data byte on serial data input (d), and driving the chip select ( s ) signal high. this instruction allows the user to change the values of the bp1 and bp0 bits which define the size of the area that is to be treated as read only, as defined in table 3: write-protected block size . the contents of the bp1, bp0 bits are u pdated after the completion of the wrsr instruction, including the write cycle (t w ). the write status register (wrsr) instruction has no effect on the b6, b5, b4, b1 and b0 bits in the status register (see table 2: status register format ). bits b7, b6, b5, b4 are always read as 1. the status register functionality is detailed in section 3.4.2: status register and data protection . the instruction is not accepted, and is not executed, under the following conditions: ? if the write enable latch (wel) bit has not been set to 1 (by executing a write enable instruction just before) ? if a write cycle is already in progress ? if the device has not been deselected, by ch ip select (s) being driven high, after the eighth bit, b0, of the data byte has been latched in ? if write protect (w) is low during the wrsr command (instruction, address and data) figure 8. write status register (wrsr) sequence # $ !)d 3 1 (igh)mpedance )nstruction 3tatus 2egister)n -3"
instructions M95040-A125 m95040-a145 18/41 docid024225 rev 6 4.5 read from memory array (read) the read instruction is used to read the content of the memory. as shown in figure 9 , to send this instruction to the device, chip select ( s ) is first driven low. the bits of the instruction byte and address byte are then shifted in, on serial data input (d). the most significant address bit, a8, is incorporated as bit b3 of the instruction byte, as shown in table 5: instruction set . the address is loaded into an internal address register, and the byte of data at that address is shifted out, on serial data output (q). if chip select ( s ) continues to be driven low, the internal address register is automatically incremented, and the next byte of data is shifted out. the whole memory can therefore be read with a single read instruction. when the highest address is reached, the addr ess counter rolls over to zero, a llowing the read cycle to be continued indefinitely. the read cycle is terminated by driving chip select ( s ) high at any time when the data bits are shifted out on serial data output (q). the instruction is not accepted, and is not execut ed, if a write cycle is currently in progress. figure 9. read from memory array (read) sequence 1. depending on the memory size, as shown in table 6 , the most significant address bits are don?t care. # $ !)% 3 1 ! ! ! ! ! ! ! ! ! (igh)mpedance $ata/ut )nstruction "yte!ddress
docid024225 rev 6 19/41 M95040-A125 m95040-a145 instructions 40 4.6 write to memo ry array (write) the write instruction is used to write new data in the memory. as shown in figure 10 , to send this instruction to the device, chip select ( s ) is first driven low. the bits of the instruction byte, address byte, and at least one data byte are then shifted in (msb first), on serial data input (d). the in struction is terminated by driving chip select ( s ) high at a data byte boundary. figure 10 shows a single byte write. figure 10. byte write (write) sequence a page write is used to write several bytes insi de a page, with a single internal write cycle. for a page write, chip select ( s ) has to remain low, as shown in figure 11 , so that the next data bytes are shifted in. each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. if the address counter exceeds the page boundary (the page size is 32 byte), the intern al address pointer rolls over to the beginning of the same page where next data bytes will be written. if more than 16 byte are received, only the last 16 byte are written. for both byte write and page write, the self-timed write cycle starts from the rising edge of chip select ( s ), and continues for a period t w (as specified in table 14 ). the instruction is discarded, and is no t executed, under the following conditions: ? if a write cycle is already in progress ? if write protect (w) is low or if the address ed page is in the area protected by the block protect (bp1 and bp0) bits ? if one of the conditions defined in section 3.4.1 is not satisfied note: the self-timed write cycle t w is internally executed as a sequence of two consecutive events: [erase addressed byte(s)], followed by [program addressed byte(s)]. an erased bit is read as ?0? and a programmed bit is read as ?1?. $,' ^ y ? ? e ? ? ? ? ? e ? ? ? ? e ? ? ? ? ? ?? ?? ,]pz/u?v /v????]}v ????? ?e?? ???
instructions M95040-A125 m95040-a145 20/41 docid024225 rev 6 figure 11. page write (write) sequence # $ 3 )nstruction "yte!ddress $ata"yte # $ !)$ 3 . $ata"yte . . . . . . . $ata"yte. $ata"yte ! ! ! ! ! ! ! ! !
docid024225 rev 6 21/41 M95040-A125 m95040-a145 instructions 40 4.7 read identification page (rdid) the read identification page instruction is used to read the identification page (additional page of 16 byte which can be written and later permanently locked in read-only mode). the chip select ( s ) signal is first driven low, the bits of the instruction byte and address bytes are then shifted in (msb fi rst) on serial data input (d). address bit a8 must be 0 and the other upper address bits are don't care (it might be easier to define these bits as 0, as shown in table 6 ). the data byte pointed to by the lower address bits [a4:a0] is shifted out (msb first) on serial data output (q). the first byte addressed can be any byte within the identification page. if chip select ( s ) continues to be driven low, the internal address register is automatically incremented and the byte of data at the new address is shifted out. note that there is no roll over feature in the identification page. the address of bytes to read must not exceed the page boundary. the read cycle is terminated by driving chip select ( s ) high. the rising edge of the chip select ( s ) signal can occur at any time when the data bits are shifted out. the instruction is not accepted, and is not execut ed, if a write cycle is currently in progress. figure 12. read identification page sequence the first three bytes of the identification pa ge offer information about the device itself. please refer to section 3.5: identification page for more information. # $ -36 3 1 ! ! ! ! ! ! ! ! (igh)mpedance $ata/ut )nstruction "yte!ddress
instructions M95040-A125 m95040-a145 22/41 docid024225 rev 6 4.8 write identification page (wrid) the write identification page instruction is used to write the identification page (additional page of 16 byte which can also be permanently locked in read-only mode). the chip select signal ( s ) is first driven low, and then the bits of the instruction byte, address bytes, and at least one data byte are shifted in (msb first) on serial data input (d). address bit a8 must be 0 and the other upper address bits are don't care (it might be easier to define these bits as 0, as shown in table 6 ). the lower address bits [a4:a0] define the byte address inside the identification page. the self-timed write cycle starts from the rising edge of chip select ( s ), and continues for a period t w (as specified in table 14 ). figure 13. write identification page sequence note: the first three bytes of the identification page offer the devi ce identification code (please refer to section 3.5: identification page for more information). us ing the wrid command on these first three bytes overwrites the device identification code. the instruction is discarded, and is no t executed, under the following conditions: ? if a write cycle is already in progress ? if the block protect bits (bp1,bp0) = (1,1) ? if one of the conditions defined in section 3.4.1: protocol control is not satisfied. 4.9 read lock status (rdls) the read lock status instruction is used to read the lock status. to send this instruction to the device, chip select ( s ) first has to be driven low. the bits of the instruction byte and address bytes are then shifted in (msb first) on serial data input (d). address bit a7 must be 1; all other addre ss bits are don't care (it might be easier to define these bits as 0, as shown in table 6 ). the lock bit is the lsb (least significant bit) of the byte read on serial data output (q). it is at ?1? when the lock is active and at ?0? when the lock is not active. if chip select ( s ) continues to be driven low, the same data byte is shifted out. 069 ^ y ? ? e ? ? ? ??e??? ? e ? ? ? ? ?? ?? ,]pz/u?v /v????]}v ????? ?e?? ???
docid024225 rev 6 23/41 M95040-A125 m95040-a145 instructions 40 the read cycle is terminated by driving chip select ( s ) high. the instruction sequence is shown in figure 14 . the read lock status instruction is not accepted and not executed if a write cycle is currently in progress. figure 14. read lock status sequence 4.10 lock identifi cation page (lid) the lock identification page (lid) command is used to permanently lock the identification page in read-only mode. the lid instruction is issued by driving ch ip select (s) low, sending (msb first) the instruction code, the address and a data byte on serial data input (d), and driving chip select (s) high. in the address sent, a7 must be equal to 1. all other address bits are don't care (it might be easier to define these bits as 0, as shown in table 6 ). the data byte sent must be equal to the binary value xxxx xx1x, where x = don't care. the lid instruction is terminated by driving chip select (s) high at a data byte boundary, otherwise, the instruction is not executed. figure 15. lock id sequence # $ -36 3 1 ! ! ! ! ! ! ! ! (igh)mpedance $ata/ut )nstruction "yte!ddress d^???s ^ y ? ?e??? ?e???? ? ?? ? ?? ?? ,]pz]u?v /v????]}v ?r]???? ?e?? ??? ?e ??
instructions M95040-A125 m95040-a145 24/41 docid024225 rev 6 driving chip select ( s ) high at a byte boundary of the input data triggers the self-timed write cycle which duration is t w (specified in table 14 ). the instruction sequence is shown in figure 15 . the instruction is discarded, and is no t executed, under the following conditions: ? if a write cycle is already in progress ? if the block protect bits (bp1,bp0) = (1,1) ? if one of the conditions defined in section 3.4.1: protocol control is not satisfied.
docid024225 rev 6 25/41 M95040-A125 m95040-a145 application design recommendations 40 5 application design recommendations 5.1 supply voltage (v cc ) 5.1.1 operating supply voltage (v cc ) prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage within the specified [v cc(min) , v cc(max) ] range must be applied (see table 9 and table 10 ). this voltage must remain stable and valid unt il the end of the transmission of the instruction and, for a write instructio n, until the completion of the internal write cycle (t w ). in order to secure a stable dc supply voltage, it is recommended to decouple the v cc line with a suitable capacitor (usually of the order of 10 nf to 100 nf) close to the v cc /v ss package pins. 5.1.2 power-up conditions when the power supply is turned on, v cc continuously rises from v ss to v cc . during this time, the chip select ( s ) line is not allowed to float but should follow the v cc voltage. it is therefore recommended to connect the s line to v cc via a suitable pull-up resistor (see figure 16 ). the v cc voltage has to rise continuously from 0 v up to the minimum v cc operating voltage defined in table 12 and table 13 . in order to prevent inadvertent write operations during power-up, a power-on-reset (por) circuit is included. at power-up, the device does not re spond to any instruction until v cc reaches the internal threshold voltage (this threshold is defined in the dc characteristics tables 12 and 13 as vres). when v cc passes over the por threshold, the device is reset and in the following state: ? in the standby power mode ? deselected ? status register values: ? write enable latch (w el) bit is reset to 0. ? write in progress (wip) bit is reset to 0. ? bp1 and bp0 bits remain unchanged (non-volatile bits). ? not in the hold condition as soon as the v cc voltage has reached a stable value within [v cc (min), v cc (max)] range, the device is ready for operation.
application design recommendations M95040-A125 m95040-a145 26/41 docid024225 rev 6 5.1.3 power-down during power-down (continuous decrease in the v cc supply voltage below the minimum v cc operating voltage defined in table 12 and table 13 ), the device must be: ? deselected (chip select (s ) should be allowed to follo w the voltage applied on v cc ), ? in standby power mode (there should not be any internal write cycle in progress). 5.2 implementing d evices on spi bus figure 16 shows an example of three devices, connected to the spi bus master. only one device is selected at a time, so that only th e selected device drives the serial data output (q) line. all the other devices outputs are then in high impedance. figure 16. bus master and memory devices on the spi bus 1. the write protect (w ) and hold (hold ) signals must be driven high or low as appropriate. a pull-up resistor connected on each / s input (represented in figure 16 ) ensures that each device is not selected if the bus master leaves the / s line in the high impedance state. 5.3 error correction code (ecc x 1) the error correction code (ecc x 1) is an internal logic function which is transparent for the spi communication protocol. the ecc x 1 logic is implemented on each byte of the memory array. if a single bit out of the byte happens to be erroneous during a read op eration, the ecc x 1 detects this bit and replaces it with the correct value. the read re liability is therefore much improved. 30)busmaster 3$/ 3$) 3#+ #1$ #1$ #1$ #3 #3 #3 30)interfacewith #0/,#0(! or 30)memory device 3 7 (/,$ 222 6 ## 6 ## 6 ## 6 ## -36 6 33 30)memory device 3 7 (/,$ 30)memory device 3 7 (/,$
docid024225 rev 6 27/41 M95040-A125 m95040-a145 delivery state 40 6 delivery state the device is delivered with: ? the memory array set to all 1s (each byte = ffh), ? status register: bit bp1 =0 and bp0 =0, ? identification page: the first three bytes def ine the device identification code (value defined in table 4 ). the content of the following bytes is don?t care. 7 absolute maximum ratings stressing the device outside the ratings listed in table 7 may cause permanent damage to the device. these are stress ratings only, and o peration of the device at these, or any other conditions outside those indicated in the operat ing sections of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 7. absolute maximum ratings symbol parameter min. max. unit t stg storage temperature ?65 150 c t amr ambient operating temperature ?40 150 c t lead lead temperature during soldering see note (1) 1. compliant with jedec std j-std-020d (for small b ody, sn-pb or pb-free assembly), the st ecopack ? 7191395 specification, and the european directive on re strictions of hazardous substances (rohs directive 2011/65/eu of july 2011). c v o voltage on q pin ?0.50 v cc +0.6 v v i input voltage ?0.50 6.5 v i ol dc output current (q = 0) - 5 ma i oh dc output current (q = 1) - 5 ma v cc supply voltage ?0.50 6.5 v v esd electrostatic pulse (human body model) (2) 2. positive and negative pulses applied on pin pairs, in accordance with aec -q100-002 (compliant with ansi/esda/jedec js-001-2012, c1=100 pf, r1=1500 , r2=500 ) -4000v
dc and ac parameters M95040-A125 m95040-a145 28/41 docid024225 rev 6 8 dc and ac parameters this section summarizes the operating condi tions and the dc/ac characteristics of the device. table 8. cycling performance by byte symbol parameter test condition min. max. unit ncycle write cycle endurance ta 25 c, 1.7 v < v cc < 5.5 v - 4,000,000 write cycle (1) ta = 85 c, 1.7 v < v cc < 5.5 v - 1,200,000 ta = 125 c, 1.7 v < v cc < 5.5 v - 600,000 ta = 145 c (2) , 2.5 v < v cc < 5.5 v - 400,000 1. a write cycle is executed when either a page write, a by te write, a wrsr, a wrid or an lid instruction is decoded. when using the byte write, the page write or the wrid, refer also to section 5.3: error correction code (ecc x 1) . 2. for temperature range 4 only. table 9. operating conditions (voltage range w, temperature range 4) symbol parameter conditions min. max. unit v cc supply voltage - 2.5 5.5 v t a ambient operating temperature - ?40 145 c f c operating clock frequency 5.5 v v cc 2.5 v, capacitive load on q pin 100pf -10mhz table 10. operating conditions (voltage range r, temperature range 3) symbol parameter conditions min. max. unit v cc supply voltage - 1.7 5.5 v t a ambient operating temperature - ?40 125 c f c operating clock frequency v cc 2.5 v, capacitive load on q pin 100pf - 10 mhz v cc 1.7 v, capacitive load on q pin 100pf - 5 table 11. operating conditions (voltage range r, temperature range 3) for high-speed communications symbol parameter conditions min. max. unit v cc supply voltage - 4.5 5.5 v t a ambient operating temperature - ?40 85 c f c operating clock frequency v cc 4.5 v, capacitive load on q pin 60 pf - 20 mhz
docid024225 rev 6 29/41 M95040-A125 m95040-a145 dc and ac parameters 40 table 12. dc characteristics (voltage range w, temperature range 4) symbol parameter specific test conditions (in addition to conditions specified in table 9 ) min. max. unit c out (2) output capacitance (q) v out = 0 v - 8 pf c in (2) input capacitance v in = 0 v - 6 i li input leakage current v in = v ss or v cc -2 a i lo output leakage current s = v cc , v out = v ss or v cc -3 i cc supply current (read) v cc = 2.5 v, f c = 10 mhz, c = 0.1 v cc /0.9 v cc, q = open -2 ma v cc = 5.5 v, f c = 10 mhz, c = 0.1 v cc /0.9 v cc, q = open -4 i cc0 (1) supply current (write) 2.5 v < v cc < 5.5 v, during t w , s = v cc -2 (2) i cc1 supply current (standby power mode) t = 85 c, v cc = 2.5 v, s = v cc v in = v ss or v cc -2 a t = 85 c, v cc = 5.5 v, s = v cc v in = v ss or v cc -3 t = 125 c, v cc = 2.5 v, s = v cc v in = v ss or v cc -15 t = 125 c, v cc = 5.5 v, s = v cc v in = v ss or v cc -20 t = 145 c, v cc = 2.5 v, s = v cc v in = v ss or v cc -25 t = 145 c, v cc = 5.5 v, s = v cc v in = v ss or v cc -40 v il input low voltage - ?0.45 0.3 v cc v v ih input high voltage - 0.7 v cc v cc +1 v ol output low voltage i ol = 2 ma - 0.4 v oh output high voltage i oh = ?2 ma 0.8 v cc - v res (2) internal reset threshold voltage -0.51.5 1. average value during the write cycle (t w ) 2. characterized only, not 100% tested
dc and ac parameters M95040-A125 m95040-a145 30/41 docid024225 rev 6 table 13. dc characteristics (voltage range r, temperature range 3) symbol parameter test conditions (in addition to co nditions specified in table 10 ) min. max. unit c out (3) output capacitance (q) v out = 0 v - 8 pf c in (3) input capacitance v in = 0 v - 6 i li input leakage current v in = v ss or v cc -2 a i lo output leakage current s = v cc , v out = v ss or v cc -3 i cc supply current (read) v cc = 1.7 v, c = 0.1 v cc /0.9 v cc , q = open, f c = 5 mhz -2 ma v cc = 2.5 v, c = 0.1 v cc /0.9 v cc , q = open, f c = 10 mhz -2 v cc = 5.5 v, f c = 20 mhz (1) c = 0.1 v cc /0.9 v cc , q = open -5 i cc0 (2) supply current (write) 1.7 v v cc < 5.5 v during t w , s = v cc -2 (3) ma i cc1 supply current (standby mode) t = 85 c, v cc = 1.7 v, s = v cc, v in = v ss or v cc -1 a t = 85 c, v cc = 2.5 v, s = v cc, v in = v ss or v cc -2 t = 85 c, v cc = 5.5 v, s = v cc, v in = v ss or v cc -3 t = 125 c, v cc = 1.7 v, s = v cc, v in = v ss or v cc -15 t = 125 c, v cc = 2.5 v, s = v cc, v in = v ss or v cc -15 t = 125 c, v cc = 5.5 v, s = v cc, v in = v ss or v cc -20 v il input low voltage 1.7 v v cc < 2.5 v ?0.45 0.25 v cc v 2.5 v v cc < 5.5 v ?0.45 0.3 v cc v ih input high voltage 1.7 v v cc < 2.5 v 0.75 v cc v cc + 1 v 2.5 v v cc < 5.5 v 0.7 v cc v cc + 1 v ol output low voltage v cc = 1.7 v, i ol = 1 ma - 0.3 v v cc 2.5 v, i ol = 2 ma - 0.4 v oh output high voltage v cc = 1.7 v, i oh = 1 ma 0.8 v cc - v v cc 2.5 v, i oh = -2 ma 0.8 v cc - v res (3) internal reset threshold voltage - 0.5 1.5 v 1. when ?40 c < t < 85 c. 2. average value during the write cycle (t w ) 3. characterized only, not 100% tested
docid024225 rev 6 31/41 M95040-A125 m95040-a145 dc and ac parameters 40 table 14. ac characteristics symbol alt. parameter min. max. min. max. min. max. unit test conditions specified in table 10 test conditions specified in table 9 and table 10 test conditions specified in table 11 f c f sck clock frequency - 5 - 10 - 20 mhz t slch t css1 s active setup time 60 - 30 - 15 - ns t shch t css2 s not active setup time 60 - 30 - 15 - t shsl t cs s deselect time 90 - 40 - 20 - t chsh t csh s active hold time 60 - 30 - 15 - t chsl s not active hold time 60 - 30 - 15 - t ch (1) t clh clock high time 80 - 40 - 20 - t cl (1) t cll clock low time 80 - 40 - 20 - t clch (2) t rc clock rise time -2-2-2 s t chcl (2) t fc clock fall time - 2 - 2 - 2 t dvch t dsu data in setup time 20 - 10 - 5 - ns t chdx t dh data in hold time 20 - 10 - 10 - t hhch clock low hold time after hold not active 60 - 30 - 15 - t hlch clock low hold time after hold active 60 - 30 - 15 - t clhl clock low set-up time before hold active0-0-0- t clhh clock low set-up time before hold not active 0-0-0- t shqz (2) t dis output disable time - 80 - 40 - 20 t clqv (3) t v clock low to output valid - 80 - 40 - 20 t clqx t ho output hold time 0 - 0 - 0 - t qlqh (2) t ro output rise time - 20 - 20 - 20 t qhql (2) t fo output fall time - 20 - 20 - 20 t hhqv t lz hold high to output valid - 80 - 40 - 20 t hlqz (2) t hz hold low to output high-z - 80 - 40 - 20 t w t wc write time -4-4-4ms 1. t ch + t cl must never be lower than the sh ortest possible clock period, 1/f c (max). 2. value guaranteed by characterizati on, not 100% tested in production. 3. t clqv must be compatible with t cl (clock low time): if t su is the read setup time of the spi bus master, t cl must be equal to (or greater than) t clqv +t su .
dc and ac parameters M95040-A125 m95040-a145 32/41 docid024225 rev 6 figure 17. ac measurement i/o waveform figure 18. serial input timing figure 19. hold timing $,& 9 && 9 && 9 && 9 && ,qsxwdqg2xwsxw 7lplqj5hihuhqfh/hyhov ,qsxw/hyhov & ' $,g 6 06%,1 4 w '9&+ +ljklpshgdqfh /6%,1 w 6/&+ w &+'; w &/&+ w 6+&+ w 6+6/ w &+6+ w &+6/ w &+ w &/ w &+&/ & 4 $,f w &/+/ w +/&+ w ++&+ w &/++ w ++49 w +/4= 6 +2/'
docid024225 rev 6 33/41 M95040-A125 m95040-a145 dc and ac parameters 40 figure 20. serial output timing & 4 $,j ' $''5 /6%,1 w 6+4= w &+ w &/ w 4/4+ w 4+4/ w &+&/ w &/4; w &/49 w 6+6/ w &/&+ 6
package mechanical data M95040-A125 m95040-a145 34/41 docid024225 rev 6 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. 9.1 so8n package information figure 21. so8n ? 8-lead plas tic small outline, 150 mils body width, package outline 1. drawing is not to scale. table 15. so8n ? 8-lead plastic small outline, 150 mils body width, package mechanical data symbol millimeters inches (1) min. typ. max. min. typ. max. a - - 1.750 - - 0.0689 a1 0.100 - 0.250 0.0039 - 0.0098 a2 1.250 - - 0.0492 - - b 0.280 - 0.480 0.0110 - 0.0189 c 0.170 - 0.230 0.0067 - 0.0091 d 4.800 4.900 5.000 0.1890 0.1929 0.1969 e 5.800 6.000 6.200 0.2283 0.2362 0.2441 e1 3.800 3.900 4.000 0.1496 0.1535 0.1575 e - 1.270 - - 0.0500 - h 0.250 - 0.500 0.0098 - 0.0197 k 0 - 8 0 - 8 l 0.400 - 1.270 0.0157 - 0.0500 62$b9 ( fff e ' f ( k[? $ n pp / $ *$8*(3/$1( h $ /
docid024225 rev 6 35/41 M95040-A125 m95040-a145 package mechanical data 40 figure 22. so8n ? 8-lead plastic sm all outline, 150 mils body width, package recommended footprint 1. dimensions are expr essed in millimeters. l1 - 1.040 - - 0.0409 - ccc - - 0.100 - - 0.0039 1. values in inches are converted fr om mm and rounded to four decimal digits. table 15. so8n ? 8-lead plastic small outline, 150 mils body width, package mechanical data (continued) symbol millimeters inches (1) min. typ. max. min. typ. max. 2b621b)3b9 [
package mechanical data M95040-A125 m95040-a145 36/41 docid024225 rev 6 9.2 tssop8 package information figure 23. tssop8 ? 8-lead thin shrink sm all outline, 3 x 4.4 mm, 0.65 mm pitch, package outline 1. drawing is not to scale. table 16. tssop8 ? 8-lead thin shrink small outline, 3 x 4.4 mm, 0.65 mm pitch, package mechanical data symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. min. typ. max. min. typ. max. a - - 1.200 - - 0.0472 a1 0.050 - 0.150 0.0020 - 0.0059 a2 0.800 1.000 1.050 0.0315 0.0394 0.0413 b 0.190 - 0.300 0.0075 - 0.0118 c 0.090 - 0.200 0.0035 - 0.0079 cp - - 0.100 - - 0.0039 d 2.900 3.000 3.100 0.1142 0.1181 0.1220 e - 0.650 - - 0.0256 - e 6.200 6.400 6.600 0.2441 0.2520 0.2598 e1 4.300 4.400 4.500 0.1693 0.1732 0.1772 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - 0 - 8 0 - 8 76623$0b9 w > r e > ? ??
docid024225 rev 6 37/41 M95040-A125 m95040-a145 package mechanical data 40 9.3 wfdfpn8 package information figure 24. wfdfpn8 (mlp8) ? 8-lead, 2 x 3 mm, 0.5 mm pitch very very thin fine pitch dual flat package outline 1. drawing is not to scale. 2. the central pad (the area e2 by d2 in the above illustra tion) must be either connect ed to vss or left floating (not connected) in the end application. $<b0(b9 7rsylhz 3lq,'pdunlqj 6lghylhz 6hdwlqjsodqh %rwwrpylhz 'dwxp< 7huplqdowls 'hwdlo3= 6hh= 'hwdlo hhh / / / ( ( 1;e ' ' ( 1'[h . h ' $ $ # & h 'dwxp< eee ggg & & - - 3lq $ % ddd # [ ddd # [ fff # $ % h
package mechanical data M95040-A125 m95040-a145 38/41 docid024225 rev 6 table 17. wfpn8 (mlp8) ? 8-lead, 2 x 3 mm, 0.5 mm pitch very very thin fine pitch dual flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. min. typ. max. min. typ. max. a 0.700 0.750 0.800 0.0276 0.0295 0.0315 a1 0.025 0.045 0.065 0.0010 0.0018 0.0026 b 0.200 0.250 0.300 0.0079 0.0098 0.0118 d 1.900 2.000 2.100 0.0748 0.0787 0.0827 e 2.900 3.000 3.100 0.1142 0.1181 0.1220 e - 0.500 - - 0.0197 - l1 - - 0.150 - - 0.0059 l3 0.300 - - 0.0118 - - d2 1.050 - 1.650 0.0413 - 0.0650 e2 1.050 - 1.450 0.0413 - 0.0571 k 0.400 - - 0.0157 - - l 0.300 - 0.500 0.0118 - 0.0197 nx (2) 2. nx is the number of terminals. 8 nd (3) 3. nd is the number of terminals on ?d? sides. 4 aaa 0.150 0.0059 bbb 0.100 0.0039 ccc 0.100 0.0039 ddd 0.050 0.0020 eee (4) 4. applied for exposed die paddle and terminals. ex clude embedding part of exposed die paddle from mea- suring. 0.080 0.0031
docid024225 rev 6 39/41 M95040-A125 m95040-a145 part numbering 40 10 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. engineering samples parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st char ge. in no event, st wi ll be liable for any customer usage of these engineering samples in production. st quality has to be contacted prior to any decision to use these engineering samples to run qualification activity. table 18. ordering information scheme example: m95040-d w dw 4 t p /k device type m95 = spi serial access eeprom device function 040-d = 4 kbit (512 byte) plus identification page operating voltage w = v cc = 2.5 to 5.5 v r = v cc = 1.7 to 5.5 v package (1) 1. all packages are ecopack2 ? (rohs compliant and free of brominated, chlorinated and antimony-oxide flame retardants). mn = so8 (150 mils width) dw = tssop8 (169 mils width) mf = wfdfpn8 (2 x 3 mm) device grade 3 = ?40 to 125 c. device tested with high reliability certified flow (2) 2. the high reliability cert ified flow (hrcf) is described in quality note qnee9801. please ask your nearest st sales office for a copy. 4 = ?40 to 145 c. device tested with high reliability certified flow (2) option blank = tube packing t = tape and reel packing plating technology p or g = ecopack2 ? process letter /k = manufacturing technology code
revision history M95040-A125 m95040-a145 40/41 docid024225 rev 6 11 revision history table 19. document revision history date revision changes 05-apr-2013 1 initial release. 05-sep-2013 2 added wfdfpn8 (mf) package. removed ufdfpn8 (mlp8) package. updated: ? section 4.4: write status register (wrsr) : replaced ?bits b7, b6, b5, b4 are always read as 0? by ?bits b7, b6, b5, b4 are always read as 1? . ? note (1) under table 7: absolute maximum ratings . 11-dec-2013 3 updated figure 24: wfdfpn8 (mlp8) ? 8-lead, 2 x 3 mm, 0.5 mm pitch very very thin fine pitch dual flat package outline . document status changed from ?p reliminary data? to ?production data?. data retention modified from ?40 years at 50 c? to ?50 years at 125 c??. 26-sept-2014 4 updated note 2 below table 7: absolute maximum ratings . updated table 13: dc characteristics (voltage range r, temperature range 3) . updated table 17: wfpn8 (mlp8) ? 8-lead, 2 x 3 mm, 0.5 mm pitch very very thin fine pitch dual flat package mechanical data . updated table 18: ordering information scheme . added note 2 below figure 24: wfdfpn8 (mlp8) ? 8-lead, 2 x 3 mm, 0.5 mm pitch very very thin fine pitch dual flat package outline . 12-jan-2015 5 updated table 17: wfpn8 (mlp8) ? 8-lead, 2 x 3 mm, 0.5 mm pitch very very thin fine pitch dual flat package mechanical data updated figure 24: wfdfpn8 (mlp8) ? 8-lead, 2 x 3 mm, 0.5 mm pitch very very thin fine pitch dual flat package outline added paragraph: engineering samples on page 39 16-feb-2016 6 updated ? section 9: package mechanical data ?v cc min value.
docid024225 rev 6 41/41 M95040-A125 m95040-a145 41 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2016 stmicroelectronics ? all rights reserved

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